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Comparators are utilised by Nyquist-rate and oversampling analog to digitalconverters (ADCs) to accomplish quantization and perhaps sampling. Thus,comparators have a substantial effect on the speed and accuracy of ADCs. Thisstudy provides a revised design for a dynamic-latch-based comparator thatachieves the lowest latency, maximum area-efficient realisation, reduced powerdissipation, and low offset. The proposed circuit has been designed andsimulated using GDPK 45 nm standard CMOS-Process to operate on 100 MHz clock,at 1.2V supply voltage. Design and simulation have been carried out usingCADENCE Virtuoso EDA tool. Compared to the original design, the PDP was easilyreduced by approximately by 6% with offset voltage reduced by 8 mV withoutspeed trade-off.

Design of a Strong-Arm Dynamic-Latch based comparator with high speed, low power and low offset for SAR-ADC