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The advent of nanoscale memristors raised hopes of being able to build CMOL(CMOS/nanowire/moLecular) type ultra-dense in-memory-computing circuitarchitectures. In CMOL, nanoscale memristors would be fabricated at theintersection of nanowires. The CMOL concept can be exploited in neuromorphichardware by fabricating lower-density neurons on CMOS and placing massiveanalog synaptic connectivity with nanowire and nanoscale-memristor fabricpost-fabricated on top. However, technical problems have hindered suchdevelopments for presently available reliable commercial monolithicCMOS-memristor technologies. On one hand, each memristor needs a MOS selectortransistor in series to guarantee forming and programming operations in largearrays. This results in compound MOS-memristor synapses (called 1T1R) which areno longer synapses at the crossing of nanowires. On the other hand, memristorsdo not yet constitute highly reliable, stable analog memories for massiveanalog-weight synapses with gradual learning. Here we demonstrate a pseudo-CMOLmonolithic chip core that circumvents the two technical problems mentionedabove by (a) exploiting a CMOL-like geometrical chip layout technique toimprove density despite the 1T1R limitation, and (b) exploiting a binary weightstochastic Spike-Timing-Dependent-Plasticity (STDP) learning rule that takesadvantage of the more reliable binary memory capability of the memristors used.Experimental results are provided for a spiking neural network (SNN) CMOL-corewith 64 input neurons, 64 output neurons, and 4096 1T1R synapses, fabricated in130nm CMOS with 200nm-sized Ti/HfOx/TiN memristors on top. The CMOL-core usesquery-driven event read-out, which allows for memristor variability insensitivecomputations.

A CMOL-Like Memristor-CMOS Neuromorphic Chip-Core Demonstrating Stochastic Binary STDP