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Sampling is an important process in many GNN structures in order to trainlarger datasets with a smaller computational complexity. However, compared toother processes in GNN (such as aggregate, backward propagation), the samplingprocess still costs tremendous time, which limits the speed of training. Toreduce the time of sampling, hardware acceleration is an ideal choice. However,state of the art GNN acceleration proposal did not specify how to acceleratethe sampling process. What's more, directly accelerating traditional samplingalgorithms will make the structure of the accelerator very complicated.  In this work, we made two contributions: (1) Proposed a new neighbor sampler:CONCAT Sampler, which can be easily accelerated on hardware level whileguaranteeing the test accuracy. (2) Designed a CONCAT-sampler-accelerator basedon FPGA, with which the neighbor sampling process boosted to about 300-1000times faster compared to the sampling process without it.

Hardware Acceleration of Sampling Algorithms in Sample and Aggregate Graph Neural Networks