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In this paper, we propose TAPA, an end-to-end framework that compiles a C++task-parallel dataflow program into a high-frequency FPGA accelerator. Comparedto existing solutions, TAPA has two major advantages. First, TAPA provides aset of convenient APIs that allow users to easily express flexible and complexinter-task communication structures. Second, TAPA adopts a coarse-grainedfloorplanning step during HLS compilation for accurate pipelining of potentialcritical paths. In addition, TAPA implements several optimization techniquesspecifically tailored for modern HBM-based FPGAs. In our experiments with atotal of 43 designs, we improve the average frequency from 147 MHz to 297 MHz(a 102% improvement) with no loss of throughput and a negligible change inresource utilization. Notably, in 16 experiments we make the originallyunroutable designs achieve 274 MHz on average. The framework is available athttps://github.com/UCLA-VAST/tapa and the core floorplan module is available athttps://github.com/UCLA-VAST/AutoBridge.

TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design