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The semiconductor industry's rapid advancement pushes conventionaltwo-dimensional technology to its utmost limitations in terms of scaling,performance, and cost factors. These challenges drive the usage of 3Dtechnology in the production of various Integrated Circuits. One of thenumerous features of 3D Integration is the use of Through Silicon Vias (TSVs)for the assembly of multilayers into a single stack. This process, which wasinitially developed for memory chips, has been used afterward in manyapplications in other areas of microelectronics. The purpose of this researchis to assess the effect of 3D-TSV interconnection on the performance of MOStransistors and CMOS circuits. This is accomplished using numerical andanalytical models capable of describing the substrate coupling induced by TSVat the circuit level. The analytical approach proposed enables the study andoptimization of the performance, not only of MOS devices but also large CMOScircuits with 3D interconnects as a function of various technological andelectrical parameters.

Overview and study of the 3D-TSV interconnects induced coupling in CMOS circuits