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This paper addresses the question: Can spintronic circuits based on MagneticTunnel Junction (MTJ) transducers outperform their state-of-the-art CMOScounterparts? To this end, we use the EPFL combinational benchmark sets,synthesize them in 7 nm CMOS and in MTJ-based spintronic technologies, andcompare the two implementation methods in terms of Energy-Delay-Product (EDP).To fully utilize the technologies potential, CMOS and spintronicimplementations are built upon standard Boolean and Majority Gates,respectively. For the spintronic circuits, we assumed that domain conversion(electric/magnetic to magnetic/electric) is performed by means of MTJs and thecomputation is accomplished by domain wall based majority gates, and consideredtwo EDP estimation scenarios: (i) Uniform Benchmarking, which ignores thecircuit's internal structure and only includes domain transducers power anddelay contributions into the calculations, and (ii) Majority-Inverter-GraphBenchmarking, which also embeds the circuit structure, the associated criticalpath delay and energy consumption by DW propagation. Our results indicate thatfor the uniform case, the spintronic route is better suited for theimplementation of complex circuits with few inputs and outputs. On the otherhand, when the circuit structure is also considered via majority and invertersynthesis, our analysis clearly indicates that in order to match and eventuallyoutperform CMOS performance, MTJ efficiency has to be improved by 3-4 orders ofmagnitude. While it is clear that for the time being the MTJ-based-spintronicway cannot compete with CMOS, further transducer developments may tip thebalance, which, when combined with information non-volatility, may makespintronic implementation for certain applications that require a large numberof calculations and have a rather limited amount of interaction with theenvironment.

Perspectives and Challenges of Scaled Boolean Spintronic Circuits Based on Magnetic Tunnel Junction Transducers