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While various obfuscation methods exist in the digital domain, techniques forprotecting Intellectual Property (IP) in the analog domain are mostlyoverlooked. Understandably, analog components have a small footprint as most ofthe surface of an Integrated Circuit (IC) is digital. Yet, since they arechallenging to design and tune, they constitute a valuable IP that ought to beprotected. This paper is the first to show a method to secure analog IP byexploiting layout-based effects that are typically seen as undesirabledetractors in IC design. Specifically, we make use of the effects of Length ofOxide Diffusion and Well Proximity Effect on transistors for tuning thedevices' critical parameters (e.g., gm and Vth). Such parameters are hiddenbehind key inputs, akin to the logic locking approach for digital ICs. Theproposed technique is applied for locking an Operational TransconductanceAmplifier. In order to showcase the robustness of the achieved obfuscation, thecase studied circuit is simulated for a large number of key sets, i.e., >50Kand >300K, and the results show a wide range of degradation in open-loop gain(up to 130dB), phase margin (up to 50 deg), 3dB bandwidth (approx. 2.5MHz), andpower (approx. 1mW) of the locked circuit when incorrect keys are applied. Ourresults show the benefit of the technique and the incurred overheads. We alsojustify the non-effectiveness of reverse engineering efforts for attacking theproposed approach. More importantly, our technique employs only regulartransistors and requires neither changes to the IC fabrication process nor anyfoundry-level coordination or trust.

Leveraging Layout-based Effects for Locking Analog ICs