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Logic locking protects an IC from threats such as piracy of design IP andunauthorized overproduction throughout the IC supply chain. Out of the severaltechniques proposed by the research community, provably-secure logic locking(PSLL) has acquired a foothold due to its algorithmic and provable-securityguarantees. However, the security of these techniques is questioned byattackers that exploit the vulnerabilities arising from the hardwareimplementation. Such attacks (i) are predominantly specific to lockingtechniques and (ii) lack generality and scalability. This leads to a plethoraof attacks, and defenders, find it challenging to ascertain the security ofnewly developed PSLL techniques. Additionally, there is no repository of lockedcircuits that attackers can use to benchmark (and compare) their attacks.  In this work, we develop a generalized attack that can recover the secret keyacross different PSLL techniques. To that end, we extract functional andstructural properties depending on the hardware construction of the PSLLtechniques and develop two attacks based on the concepts of VLSI testing andBoolean transformations. We evaluate our attacks on 30,000 locked circuitsacross 14 PSLL techniques, including nine unbroken techniques. Our attackssuccessfully recover the secret key (100% accuracy) for all the techniques. Ourexperimentation across different (I) technology libraries, (ii) synthesistools, and (iii) logic optimization settings provide interesting insights. Forinstance, our attacks recover the secret key by only using the locked circuitwhen an academic synthesis tool is used. Additionally, designers can use ourattacks as a verification tool to ascertain the lower-bound security achievedby hardware implementations. We shall release our artifacts, which could helpfoster the development of future attacks and defenses in the PSLL domain.

Hide & Seek: Seeking the (Un)-Hidden key in Provably-Secure Logic Locking Techniques