English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

To mitigate the impact of noise and interference on multi-level-cell (MLC)flash memory with the use of low-density parity-check (LDPC) codes, we proposea dynamic write-voltage design scheme considering the asymmetric property ofraw bit error rate (RBER), which can obtain the optimal write voltage byminimizing a cost function. In order to further improve the decodingperformance of flash memory, we put forward a low-complexity entropy-basedread-voltage optimization scheme, which derives the read voltages by searchingfor the optimal entropy value via a log-likelihood ratio (LLR)-aware costfunction. Simulation results demonstrate the superiority of our proposeddynamic write-voltage design scheme and read-voltage optimization scheme withrespect to the existing counterparts.

Dynamic Write-Voltage Design and Read-Voltage Optimization for MLC NAND Flash Memory