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Modern high-performance computing architectures (Multicore, GPU, Manycore)are based on tightly-coupled clusters of processing elements, physicallyimplemented as rectangular tiles. Their size and aspect ratio strongly impactthe achievable operating frequency and energy efficiency, but they should be asflexible as possible to achieve a high utilization for the top-level diefloorplan. In this paper, we explore the flexibility range for ahigh-performance cluster of RISC-V cores with shared L1 memory used to buildscalable accelerators, with the goal of establishing a hierarchicalimplementation methodology where clusters can be modeled as soft tiles toachieve optimal die utilization.

Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters