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In this paper, we present an energy-efficient, yet high-speed approximatemaximally redundant signed digit (MRSD) multiplier (called AMR-MUL) based on aparallel structure. For the reduction stage, we suggest several approximateFull-Adder (FA) reduction cells with average positive and negative errorsobtained by simplifying the structure of an exact FA cell. The optimumselection of these cells for each partial product reduction stage provides thelowest possible error, turning this task into a design space explorationproblem. We also provide a branch-and-bound design space exploration algorithmto find the optimal assignment of reduction cells based on a predefinedconstraint (i.e., the width of the approximate part) by the user. Theeffectiveness of the proposed (Radix-16) multiplier design is assessed underdifferent digit counts and approximate border column. The results show that theenergy consumption of the MRSD multiplier is reduced by 7x at the cost of a1.6% accuracy loss.

AMR-MUL: An Approximate Maximally Redundant Signed Digit Multiplier