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Spike detection plays a central role in neural data processing andbrain-machine interfaces (BMIs). A challenge for future-generation implantableBMIs is to build a spike detector that features both low hardware cost and highperformance. In this work, we propose a novel hardware-efficient andhigh-performance spike detector for implantable BMIs. The proposed design isbased on a dual-detector architecture with adaptive threshold estimation. Thedual-detector comprises two separate TEO-based detectors that distinguish aspike occurrence based on its discriminating features in both high and lownoise scenarios. We evaluated the proposed spike detection algorithm on theWave Clus dataset. It achieved an average detection accuracy of 98.9%, and over95% in high-noise scenarios, ensuring the reliability of our method. Whenrealized in hardware with a sampling rate of 16kHz and 7-bits resolution, thedetection accuracy is 97.4%. Designed in 65nm TSMC process, a 256-channeldetector based on this architecture occupies only 682$\mu m^2$ /Channel andconsumes 0.07$\mu$W/Channel, improving over the state-of-the-art spikedetectors by 39.7% in power consumption and 78.8% in area, while maintaining ahigh accuracy.

An Accurate and Hardware-Efficient Dual Spike Detector for Implantable Neural Interfaces