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This paper presents a novel encoding method for fine time data of a tappeddelay line (TDL) time-to-digital Converter (TDC). It is based ondivide-and-conquer strategy, and has the advantage of significantly reducinglogic resource utilization while retaining low dead-time performance.Furthermore, the problem of high bubble depth in advanced devices can beresolved with this method. Four examples are demonstrated, which wereimplemented in a Xilinx Artix-7 Field Programmable Gate Array (FPGA) device,and encoding method presented in this paper was employed to encode fine timedata for normal TDL TDC, a half-length delay line TDC, and double-edge andfour-edge wave union TDCs. Compared with TDCs from the latest published papersthat adopt traditional encoders, the logic utilization of TDCs in this paperwere reduced by a factor of 45% to 70% in different situations, while theencoding dead time can be restricted in one clock cycle. Acceptable resolutionsof the demonstrated TDCs were also obtained, proving the functionality of theencoding method.

A low dead time, resource efficient encoding method for FPGA based high-resolution TDL TDCs