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Conventional neural structures tend to communicate through analog quantitiessuch as currents or voltages, however, as CMOS devices shrink and supplyvoltages decrease, the dynamic range of voltage/current-domain analog circuitsbecomes narrower, the available margin becomes smaller, and noise immunitydecreases. More than that, the use of operational amplifiers (op-amps) andcontinuous-time or clocked comparators in conventional designs leads to highenergy consumption and large chip area, which would be detrimental to buildingspiking neural networks. In view of this, we propose a neural structure forgenerating and transmitting time-domain signals, including a neuron module, asynapse module, and two weight modules. The proposed neural structure is drivenby a leakage current of MOS transistors and uses an inverter-based comparatorto realize a firing function, thus providing higher energy and area efficiencycompared to conventional designs. The proposed neural structure is fabricatedusing TSMC 65 nm CMOS technology. The proposed neuron and synapse occupy thearea of 127 {\mu}m^{ 2} and 231 {\mu}m^{ 2}, respectively, while achievingmillisecond time constants. Actual chip measurements show that the proposedstructure implements the temporal signal communication function withmillisecond time constants, which is a critical step toward hardware reservoircomputing for human-computer interaction. Simulation results of thespiking-neural network for reservoir computing with the behavioral model of theproposed neural structure demonstrate the learning function.

CMOS-based area-and-power-efficient neuron and synapse circuits for time-domain analog spiking neural networks