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Graphics processing units (GPUs) are now considered the leading hardware toaccelerate general-purpose workloads such as AI, data analytics, and HPC. Overthe last decade, researchers have focused on demystifying and evaluating themicroarchitecture features of various GPU architectures beyond what vendorsreveal. This line of work is necessary to understand the hardware better andbuild more efficient workloads and applications. Many works have studied therecent Nvidia architectures, such as Volta and Turing, comparing them to theirsuccessor, Ampere. However, some microarchitecture features, such as the clockcycles for the different instructions, have not been extensively studied forthe Ampere architecture. In this paper, we study the clock cycles perinstructions with various data types found in the instruction-set architecture(ISA) of Nvidia GPUs. Using microbenchmarks, we measure the clock cycles forPTX ISA instructions and their SASS ISA instructions counterpart. we furthercalculate the clock cycle needed to access each memory unit. We also demystifythe new version of the tensor core unit found in the Ampere architecture byusing the WMMA API and measuring its clock cycles per instruction andthroughput for the different data types and input shapes. The results found inthis work should guide software developers and hardware architects.Furthermore, the clock cycles per instructions are widely used by performancemodeling simulators and tools to model and predict the performance of thehardware.

Demystifying the Nvidia Ampere Architecture through Microbenchmarking and Instruction-level Analysis