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Ring Learning With Error (RLWE) algorithm is used in Post QuantumCryptography (PQC) and Homomorphic Encryption (HE) algorithm. The existingclassical crypto algorithms may be broken in quantum computers. The adversariescan store all encrypted data. While the quantum computer will be available,these encrypted data can be exposed by the quantum computer. Therefore, the PQCalgorithms are an essential solution in recent applications. On the other hand,the HE allows operations on encrypted data which is appropriate for gettingservices from third parties without revealing confidential plain-texts. TheFPGA based PQC and HE hardware accelerators like RLWE is much cost-effectivethan processor based platform and Application Specific Integrated Circuit(ASIC). FPGA based hardware accelerators still consume more power compare toASIC based design. Near Threshold Computation (NTC) may be a convenientsolution for FPGA based RLWE implementation. In this paper, we have implementedRLWE hardware accelerator which has 14 subcomponents. This paper createsclusters based on the critical path of all 14 subcomponents. Each cluster isimplemented in an FPGA partition which has the same biasing voltage$V_{ccint}$. The clusters that have higher critical paths use higher Vccint toavoid timing failure. The clusters have lower critical paths use lower biasingvoltage Vccint. This voltage scaled, partitioned RLWE can save ~6% and ~11%power in Vivado and VTR platform respectively. The resource usage andthroughput of the implemented RLWE hardware accelerator is comparatively betterthan existing literature.

Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Post Quantum Cryptography on Reconfigurable Architecture