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Process variations and device aging impose profound challenges for circuitdesigners. Without a precise understanding of the impact of variations on thedelay of circuit paths, guardbands, which keep timing violations at bay, cannotbe correctly estimated. This problem is exacerbated for advanced technologynodes, where transistor dimensions reach atomic levels and established marginsare severely constrained. Hence, traditional worst-case analysis becomesimpractical, resulting in intolerable performance overheads. Contrarily,process-variation/aging-aware static timing analysis (STA) equips designerswith accurate statistical delay distributions. Timing guardbands that aresmall, yet sufficient, can then be effectively estimated. However, suchanalysis is costly as it requires intensive Monte-Carlo simulations. Further,it necessitates access to confidential physics-based aging models to generatethe standard-cell libraries required for STA.  In this work, we employ graph neural networks (GNNs) to accurately estimatethe impact of process variations and device aging on the delay of any pathwithin a circuit. Our proposed GNN4REL framework empowers designers to performrapid and accurate reliability estimations without accessing transistor models,standard-cell libraries, or even STA; these components are all incorporatedinto the GNN model via training by the foundry. Specifically, GNN4REL istrained on a FinFET technology model that is calibrated against industrial 14nmmeasurement data. Through our extensive experiments on EPFL and ITC-99benchmarks, as well as RISC-V processors, we successfully estimate delaydegradations of all paths -- notably within seconds -- with a mean absoluteerror down to 0.01 percentage points.

GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation