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Recent efforts for improving the performance of neural network (NN)accelerators that meet today's application requirements have given rise to anew trend of logic-based NN inference relying on fixed function combinationallogic. Mapping such large Boolean functions with many input variables andproduct terms to digital signal processors (DSPs) on Field-programmable gatearrays (FPGAs) needs a novel framework considering the structure and thereconfigurability of DSP blocks during this process. The proposed methodologyin this paper maps the fixed function combinational logic blocks to a set ofBoolean functions where Boolean operations corresponding to each function aremapped to DSP devices rather than look-up tables (LUTs) on the FPGAs to takeadvantage of the high performance, low latency, and parallelism of DSP blocks.% This paper also presents an innovative design and optimization methodologyfor compilation and mapping of NNs, utilizing fixed function combinationallogic to DSPs on FPGAs employing high-level synthesis flow. % Our experimentalevaluations across several \REVone{datasets} and selected NNs demonstrate thecomparable performance of our framework in terms of the inference latency andoutput accuracy compared to prior art FPGA-based NN accelerators employingDSPs.

Efficient Compilation and Mapping of Fixed Function Combinational Logic  onto Digital Signal Processors Targeting Neural Network Inference and  Utilizing High-level Synthesis