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We propose Sectored DRAM, a new, low-overhead DRAM substrate that reduceswasted energy by enabling fine-grained DRAM data transfers and DRAM rowactivation. Sectored DRAM leverages two key ideas to enable fine-grained datatransfers and row activation at low chip area cost. First, a cache blocktransfer between main memory and the memory controller happens in a fixednumber of clock cycles where only a small portion of the cache block (a word)is transferred in each cycle. Sectored DRAM augments the memory controller andthe DRAM chip to execute cache block transfers in a variable number of clockcycles based on the workload access pattern with minor modifications to thememory controller's and the DRAM chip's circuitry. Second, a large DRAM row, bydesign, is already partitioned into smaller independent physically isolatedregions. Sectored DRAM provides the memory controller with the ability toactivate each such region based on the workload access pattern via smallmodifications to the DRAM chip's array access circuitry. Activating smallerregions of a large row relaxes DRAM power delivery constraints and allows thememory controller to schedule DRAM accesses faster.  Compared to a system with coarse-grained DRAM, Sectored DRAM reduces the DRAMenergy consumption of highly-memory-intensive workloads by up to (on average)33% (20%) while improving their performance by up to (on average) 36% (17%).Sectored DRAM's DRAM energy savings, combined with its system performanceimprovement, allows system-wide energy savings of up to 23%. Sectored DRAM'sDRAM chip area overhead is 1.7% the area of a modern DDR4 chip. We hope andbelieve that Sectored DRAM's ideas and results will help to enable moreefficient and high-performance memory systems. To this end, we open sourceSectored DRAM at https://github.com/CMU-SAFARI/Sectored-DRAM.

Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture