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The memory controller is in charge of managing DRAM maintenance operations(e.g., refresh, RowHammer protection, memory scrubbing) in current DRAM chips.Implementing new maintenance operations often necessitates modifications in theDRAM interface, memory controller, and potentially other system components.Such modifications are only possible with a new DRAM standard, which takes along time to develop, leading to slow progress in DRAM systems.  In this paper, our goal is to 1) ease, and thus accelerate, the process ofenabling new DRAM maintenance operations and 2) enable more efficient in-DRAMmaintenance operations. Our idea is to set the memory controller free frommanaging DRAM maintenance. To this end, we propose Self-Managing DRAM (SMD), anew low-cost DRAM architecture that enables implementing new in-DRAMmaintenance mechanisms (or modifying old ones) with no further changes in theDRAM interface, memory controller, or other system components. We use SMD toimplement new in-DRAM maintenance mechanisms for three use cases: 1) periodicrefresh, 2) RowHammer protection, and 3) memory scrubbing. We show that SMDenables easy adoption of efficient maintenance mechanisms that significantlyimprove the system performance and energy efficiency while providing higherreliability compared to conventional DDR4 DRAM. A combination of SMD-basedmaintenance mechanisms that perform refresh, RowHammer protection, and memoryscrubbing achieve 7.6% speedup and consume 5.2% less DRAM energy on averageacross 20 memory-intensive four-core workloads. We make SMD source code openlyand freely available at https://github.com/CMU-SAFARI/SelfManagingDRAM.

Self-Managing DRAM: A Low-Cost Framework for Enabling Autonomous and Efficient in-DRAM Operations