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Deep neural networks (DNN) have been proved for its effectiveness in variousareas such as classification problems, image processing, video segmentation,and speech recognition. The accelerator-in-memory (AiM) architectures are apromising solution to efficiently accelerate DNNs as they can avoid the memorybottleneck of the traditional von Neumann architecture. As the main memory isusually DRAM in many systems, a highly parallel multiply-accumulate (MAC) arraywithin the DRAM can maximize the benefit of AiM by reducing both the distanceand amount of data movement between the processor and the main memory. Thispaper presents an analog MAC array based AiM architecture named MAC-DO. Incontrast with previous in-DRAM accelerators, MAC-DO makes an entire DRAM arrayparticipate in MAC computations simultaneously without idle cells, leading tohigher throughput and energy efficiency. This improvement is made possible byexploiting a new analog computation method based on charge steering. Inaddition, MAC-DO innately supports multi-bit MACs with good linearity. MAC-DOis still compatible with current 1T1C DRAM technology without any modificationsof a DRAM cell and array. A MAC-DO array can accelerate matrix multiplicationsbased on output stationary mapping and thus supports most of the computationsperformed in DNNs. Our evaluation using transistor-level simulation shows thata test MAC-DO array with 16 x 16 MAC-DO cells achieves 188.7 TOPS/W, and shows97.07% Top-1 accuracy for MNIST dataset without retraining.

MAC-DO: Charge Based Multi-Bit Analog In-Memory Accelerator Compatible with DRAM Using Output Stationary Mapping