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Worst-Case Execution Time (WCET) is a key component for the verification ofcritical real-time applications. Yet, even the simplest microprocessorsimplement pipelines with concurrently-accessed resources, such as the memorybus shared by fetch and memory stages. Although their in-order pipelines are,by nature, very deterministic, the bus can cause out-of-order accesses to thememory and, therefore, timing anomalies: local timing effects that can haveglobal effects but that cannot be easily composed to estimate the global WCET.To cope with this situation, WCET analyses have to generate importantover-estimations in order to preserve safety of the computed times or have toexplicitly track all possible executions. In the latter case, the presence ofout-of-order behavior leads to a combinatorial blowup of the number of pipelinestates for which efficient state abstractions are difficult to design. Thispaper proposes instead a compact and exact representation of the timings in thepipeline, using eXecution Decision Diagram (XDD) [1]. We show how XDD can beused to model pipeline states all along the execution paths by leveraging thealgebraic properties of XDD. This computational model allows to compute theexact temporal behavior at control flow graph level and is amenable toefficiently and precisely support WCET calculation in presence of out-of-orderbus accesses. This model is finally experimented on the TACLe benchmark suiteand we observe good performance making this approach appropriate for industrialapplications.

Computing Execution Times with eXecution Decision Diagrams in the Presence of Out-Of-Order Resources