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Low-precision formats have recently driven major breakthroughs in neuralnetwork (NN) training and inference by reducing the memory footprint of the NNmodels and improving the energy efficiency of the underlying hardwarearchitectures. Narrow integer data types have been vastly investigated for NNinference and have successfully been pushed to the extreme of ternary andbinary representations. In contrast, most training-oriented platforms use atleast 16-bit floating-point (FP) formats. Lower-precision data types such as8-bit FP formats and mixed-precision techniques have only recently beenexplored in hardware implementations. We present MiniFloat-NN, a RISC-Vinstruction set architecture extension for low-precision NN training, providingsupport for two 8-bit and two 16-bit FP formats and expanding operations. Theextension includes sum-of-dot-product instructions that accumulate the resultin a larger format and three-term additions in two variations: expanding andnon-expanding. We implement an ExSdotp unit to efficiently support in hardwareboth instruction types. The fused nature of the ExSdotp module preventsprecision losses generated by the non-associativity of two consecutive FPadditions while saving around 30% of the area and critical path compared to acascade of two expanding fused multiply-add units. We replicate the ExSdotpmodule in a SIMD wrapper and integrate it into an open-source floating-pointunit, which, coupled to an open-source RISC-V core, lays the foundation forfuture scalable architectures targeting low-precision and mixed-precision NNtraining. A cluster containing eight extended cores sharing a scratchpadmemory, implemented in 12 nm FinFET technology, achieves up to 575 GFLOPS/Wwhen computing FP8-to-FP16 GEMMs at 0.8 V, 1.26 GHz.

MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V cores