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Neuromorphic vision is a rapidly growing field with numerous applications inthe perception systems of autonomous vehicles. Unfortunately, due to thesensors working principle, there is a significant amount of noise in the eventstream. In this paper we present a novel algorithm based on an IIR filtermatrix for filtering this type of noise and a hardware architecture that allowsits acceleration using an SoC FPGA. Our method has a very good filteringefficiency for uncorrelated noise - over 99% of noisy events are removed. Ithas been tested for several event data sets with added random noise. Wedesigned the hardware architecture in such a way as to reduce the utilisationof the FPGA's internal BRAM resources. This enabled a very low latency and athroughput of up to 385.8 MEPS million events per second.The proposed hardwarearchitecture was verified in simulation and in hardware on the Xilinx ZynqUltrascale+ MPSoC chip on the Mercury+ XU9 module with the Mercury+ ST1 baseboard.

Hardware architecture for high throughput event visual data filtering with matrix of IIR filters algorithm