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Networks-on-Chips (NoCs) recently became widely used, from multi-core CPUs toedge-AI accelerators. Emulation on FPGAs promises to accelerate their RTLmodeling compared to slow simulations. However, realistic test stimuli arechallenging to generate in hardware for diverse applications. In other words,both a fast and flexible design framework is required. The most promisingsolution is hybrid emulation, in which parts of the design are simulated insoftware, and the other parts are emulated in hardware. This paper proposes anovel hybrid emulation framework called EmuNoC. We introduce aclock-synchronization method and software-only packet generation that improvesthe emulation speed by 36.3x to 79.3x over state-of-the-art frameworks whileretaining the flexibility of a pure-software interface for stimuli simulation.We also increased the area efficiency to model up to an NoC with 169 routers ona single FPGA, while previous frameworks only achieved 64 routers.

EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs