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Modern and future processors need to remain functionally correct in thepresence of permanent faults to sustain scaling benefits and limit fieldreturns. This paper presents a combined analytical and microarchitecturalsimulation-based framework called INTERPLAY, that can rapidly predict, atdesign-time, the performance degradation expected from a processor employingway-disabling to handle permanent faults in caches while in-the-field. Theproposed model can predict a program's performance with an accuracy of up to98.40% for a processor with a two-level cache hierarchy, when multiple cachessuffer from faults and need to disable one or more of their ways. INTERPLAY is9.2x faster than an exhaustive simulation approach since it only needs thetraining simulation runs for the single-cache way-disabling configurations topredict the performance for any multi-cache way-disabling configuration.

INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling