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We compare N*N quaternary digit and 2N*2N bit CNTFET multipliers in terms ofWorst case delay, Chip area, Power and Power Delay Product (PDP) for N=1, N=2and N=4. Both multipliers use Wallace reduction trees. HSpice simulations with32-nm CNTFET parameters shows that the binary implementations are always moreefficient: the 1*1 quit multiplier is far more complex than a 1*1 bitmultiplier (AND gate) and generate both product and a carry terms. Even withhalf number of terms, the quaternary reduction tree has the same number ofterms than the binary one, and uses quaternary adders that are also morecomplicated than the binary ones. The quaternary multipliers have larger worstcase delays, more power dissipation and far more chip areas than the binaryones computing the same amount of information.

CNTFET quaternary multipliers are less efficient than the corresponding binary ones