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Realizing compact and scalable Ising machines that are compatible withCMOS-process technology is crucial to the effectiveness and practicality ofusing such hardware platforms for accelerating computationally intractableproblems. Besides the need for realizing compact Ising spins, theimplementation of the coupling network, which describes the spin interaction,is also a potential bottleneck in the scalability of such platforms. Therefore,in this work, we propose an Ising machine platform that exploits the novelbehavior of compact bi-stable CMOS-latches (cross-coupled inverters) asclassical Ising spins interacting through highly scalable and CMOS-processcompatible ferroelectric-HfO2-based Ferroelectric FETs (FeFETs) which act ascoupling elements. We experimentally demonstrate the prototype building blocksof this system, and evaluate the behavior of the scaled system usingsimulations. We project that the proposed architecture can compute Isingsolutions with an efficiency of ~1.04 x 10^8 solutions/W/second. Our work notonly provides a pathway to realizing CMOS-compatible designs but also toovercoming their scaling challenges.

CMOS-Compatible Ising Machines built using Bistable Latches Coupled through Ferroelectric Transistor Arrays