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Recent advances in logic schemes and fabrication processes have renewedinterest in using superconductor electronics for energy-efficient computing andquantum control processors. However, scalable superconducting memory stillposes a challenge. To address this issue, we present an alternative toapproaches that solely emphasize storage cell miniaturization by exploiting theminimal attenuation and dispersion properties of superconducting passivetransmission lines to develop a delay-line memory system. This fullysuperconducting design operates at speeds between 20 GHz and 100 GHz, with$\pm$24\% and $\pm$13\% bias margins, respectively, and demonstrates datadensities in the 10s of Mbit/cm$^2$ with the MIT Lincoln Laboratory SC2fabrication process. Additionally, the circulating nature of this design allowsfor minimal control circuitry, eliminates the need for data splitting andmerging, and enables inexpensive implementations of sequential access andcontent-addressable memories. Further advances in fabrication processes suggestdata densities of 100s of Mbit/cm$^2$ and beyond

Addressable Superconductor Integrated Circuit Memory from Delay Lines