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The emergence of high-bandwidth memory (HBM) brings new opportunities toboost the performance of sorting acceleration on FPGAs, which wasconventionally bounded by the available off-chip memory bandwidth. However, itis nontrivial for designers to fully utilize this immense bandwidth. First, theexisting sorter designs cannot be directly scaled at the increasing rate ofavailable off-chip bandwidth, as the required on-chip resource usage grows at amuch faster rate and would bound the sorting performance in turn. Second,designers need an in-depth understanding of HBM characteristics to effectivelyutilize the HBM bandwidth. To tackle these challenges, we present TopSort, anovel two-phase sorting solution optimized for HBM-based FPGAs. In the firstphase, 16 merge trees work in parallel to fully utilize 32 HBM channels. In thesecond phase, TopSort reuses the logic from phase one to form a wider mergetree to merge the partially sorted results from phase one. TopSort also adoptsHBM-specific optimizations to reduce resource overhead and improve bandwidthutilization. TopSort can sort up to 4 GB data using all 32 HBM channels, withan overall sorting performance of 15.6 GB/s. TopSort is 6.7x and 2.2x fasterthan state-of-the-art CPU and FPGA sorters.

TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs