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In this paper, we investigate how field programmable gate arrays can serve ashardware accelerators for real-time semantic segmentation tasks relevant forautonomous driving. Considering compressed versions of the ENet convolutionalneural network architecture, we demonstrate a fully-on-chip deployment with alatency of 4.9 ms per image, using less than 30% of the available resources ona Xilinx ZCU102 evaluation board. The latency is reduced to 3 ms per image whenincreasing the batch size to ten, corresponding to the use case where theautonomous vehicle receives inputs from multiple cameras simultaneously. Weshow, through aggressive filter reduction and heterogeneous quantization-awaretraining, and an optimized implementation of convolutional layers, that thepower consumption and resource utilization can be significantly reduced whilemaintaining accuracy on the Cityscapes dataset.

Real-time semantic segmentation on FPGAs for autonomous vehicles with hls4ml