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Calculating the most efficient schedule of work in a neural network compileris a difficult task. There are many parameters to be accounted for that canpositively or adversely affect that schedule depending on their configuration -How work is shared between distributed targets, the subdivision of tensors tofit in memory, toggling the enablement of optimizations, etc. Traditionally,neural network compilers determine how to set these values by building a graphof choices and choosing the path with minimal 'cost'. These choices and theircorresponding costs are usually determined by an algorithm crafted by engineerswith a deep knowledge of the target platform. However, when the amount ofoptions available to a compiler is large, it is very difficult to ensure thatthese models consistently produce an optimal schedule for all scenarios, whilststill completing compilation in an acceptable timeframe. This paper presents'VPUNN' - a neural network-based cost model trained on low-level task profilingthat consistently outperforms the state-of-the-art cost modeling in Intel'sline of VPU processors.

Towards Optimal VPU Compiler Cost Modeling by using Neural Networks to Infer Hardware Performances