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Computing-in-memory (CIM) has attracted significant attentions in recentyears due to its massive parallelism and low power consumption. However,current CIM designs suffer from large area overhead of small CIM macros and badprogrammablity for model execution. This paper proposes a programmable CIMprocessor with a single large sized CIM macro instead of multiple smaller onesfor power efficient computation and a flexible instruction set to supportvarious binary 1-D convolution Neural Network (CNN) models in an easy way.Furthermore, the proposed architecture adopts the pooling write-back method tosupport fused or independent convolution/pooling operations to reduce 35.9\% oflatency, and the flexible ping-pong feature SRAM to fit different feature mapsizes during layer-by-layer execution.The design fabricated in TSMC 28nmtechnology achieves 150.8 GOPS throughput and 885.86 TOPS/W power efficiency at10 MHz when executing our binary keyword spotting model, which has higher powerefficiency and flexibility than previous designs.

PSCNN: A 885.86 TOPS/W Programmable SRAM-based Computing-In-Memory Processor for Keyword Spotting