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Today's systems have diverse needs that are difficult to address usingone-size-fits-all commodity DRAM. Unfortunately, although system designers cantheoretically adapt commodity DRAM chips to meet their particular design goals(e.g., by reducing access timings to improve performance, implementingsystem-level RowHammer mitigations), we observe that designers today lacksufficient insight into commodity DRAM chips' reliability characteristics toimplement these techniques in practice. In this work, we make a case for DRAMmanufacturers to provide increased transparency into key aspects of DRAMreliability (e.g., basic chip design properties, testing strategies). Doing soenables system designers to make informed decisions to better adapt commodityDRAM to meet modern systems' needs while preserving its cost advantages.  To support our argument, we study four ways that system designers can adaptcommodity DRAM chips to system-specific design goals: (1) improving DRAMreliability; (2) reducing DRAM refresh overheads; (3) reducing DRAM accesslatency; and (4) mitigating RowHammer attacks. We observe that adoptingsolutions for any of the four goals requires system designers to makeassumptions about a DRAM chip's reliability characteristics. These assumptionsdiscourage system designers from using such solutions in practice due to thedifficulty of both making and relying upon the assumption.  We identify DRAM standards as the root of the problem: current standardsrigidly enforce a fixed operating point with no specifications for how a systemdesigner might explore alternative operating points. To overcome this problem,we introduce a two-step approach that reevaluates DRAM standards with a focuson transparency of DRAM reliability so that system designers are encouraged tomake the most of commodity DRAM technology for both current and future DRAMchips.

A Case for Transparent Reliability in DRAM Systems