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Ternary content addressable memories (TCAMs) are commonly used to implementIP lookup, but suffer from high power and area costs. Thus TCAM included inmodern chips is limited and can support moderately large datasets in datacenters and enterprises, but fails to scale to backbone WAN databases ofmillions of prefixes. IPv6 deployment also makes it harder to deploy TCAMsbecause of the larger prefixes used in the 128-bit address space. While thecombination of algorithmic techniques and TCAM has been proposed before forreducing power consumption or update costs(e.g., CoolCAM [32] and TreeCAM[28]), we focus on reducing TCAM bits using a scheme we call MashUp that caneasily be implemented in modern reconfigurable pipeline chips such as Tofino-3.MashUp uses a new technique, tiling trees, which takes into account TCAM grain(tile) sizes. When applied to a publicly available IPv6 dataset using Tofino-3TCAM grain sizes (44 by 512), there was a 2X reduction in TCAM required.Further, if we mix TCAM and SRAM using a new technique we call nodehybridization, MashUp decreases TCAM bits by 4.5X for IPv6, and by 7.5X forIPv4, allowing wide area databases of 900,000 prefixes to be supported byTofino-3 and similar chips

MashUp: Scaling TCAM-based IP Lookup to Larger Databases by Tiling Trees