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Decision trees are considered one of the most powerful tools for dataclassification. Accelerating the decision tree search is crucial foron-the-edge applications that have limited power and latency budget. In thispaper, we propose a Content Addressable Memory (CAM) Compiler for Decision Tree(DT) inference acceleration. We propose a novel "adaptive-precision" schemethat results in a compact implementation and enables an efficient bijectivemapping to Ternary Content Addressable Memories while maintaining highinference accuracies. In addition, a Resistive-CAM (ReCAM) functionalsynthesizer is developed for mapping the decision tree to the ReCAM andperforming functional simulations for energy, latency, and accuracyevaluations. We study the decision tree accuracy under hardware non-idealitiesincluding device defects, manufacturing variability, and input encoding noise.We test our framework on various DT datasets including \textit{Give Me SomeCredit}, \textit{Titanic}, and \textit{COVID-19}. Our results reveal up to{42.4\%} energy savings and up to 17.8x better energy-delay-area productcompared to the state-of-art hardware accelerators, and up to 333 milliondecisions per sec for the pipelined implementation.

DT2CAM: A Decision Tree to Content Addressable Memory Framework