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Undoubtedly faster, larger and lower power per bit, but just how do you goabout interfacing a DDR3 SDRAM DIMM to an FPGA? The DDR3 standard addresses thefaster, more bandwidth and lower power per bit need, but it introduces newdesign challenges in addition to challenges introduced by DDR2 ODT, slew ratederating, etc. The DDR3 fly-by topology requirement means customers designingDDR3 memories must now account for write leveling and read de-skew on the PCB.This paper will cover modeling, simulation, and physical layout approachesrequired to meet JEDEC-defined termination and tight timing requirements fordesigning DDR3 memory interfaces on PCB systems.

Challenges in implementing DDR3 memory interface on PCB systems: a methodology for interfacing DDR3 SDRAM DIMM to an FPGA