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Edge-computing requires high-performance energy-efficient embedded systems.Fixed-function or custom accelerators, such as FFT or FIR filter engines, arevery efficient at implementing a particular functionality for a given set ofconstraints. However, they are inflexible when facing application-wideoptimizations or functionality upgrades. Conversely, programmable cores offerhigher flexibility, but often with a penalty in area, performance, and, aboveall, energy consumption. In this paper, we propose VWR2A, an architecture thatintegrates high computational density and low power memory structures (i.e.,very-wide registers and scratchpad memories). VWR2A narrows the energy gap withsimilar or better performance on FFT kernels with respect to an FFTaccelerator. Moreover, VWR2A flexibility allows to accelerate multiple kernels,resulting in significant energy savings at the application level.

VWR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices