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Over the last three decades, innovations in the memory subsystem wereprimarily targeted at overcoming the data movement bottleneck. In this paper,we focus on a specific market trend in memory technology: 3D-stacked memory andcaches. We investigate the impact of extending the on-chip memory capabilitiesin future HPC-focused processors, particularly by 3D-stacked SRAM. First, wepropose a method oblivious to the memory subsystem to gauge the upper-bound inperformance improvements when data movement costs are eliminated. Then, usingthe gem5 simulator, we model two variants of a hypothetical LARge Cacheprocessor (LARC), fabricated in 1.5 nm and enriched with high-capacity3D-stacked cache. With a volume of experiments involving a broad set ofproxy-applications and benchmarks, we aim to reveal how HPC CPU performancewill evolve, and conclude an average boost of 9.56x for cache-sensitive HPCapplications, on a per-chip basis. Additionally, we exhaustively document ourmethodological exploration to motivate HPC centers to drive their owntechnological agenda through enhanced co-design.

At the Locus of Performance: Quantifying the Effects of Copious 3D-Stacked Cache on HPC Workloads