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Several manufacturers have already started to commercialize near-bankProcessing-In-Memory (PIM) architectures. Near-bank PIM architectures placesimple cores close to DRAM banks and can yield significant performance andenergy improvements in parallel applications by alleviating data access costs.Real PIM systems can provide high levels of parallelism, large aggregate memorybandwidth and low memory access latency, thereby being a good fit to acceleratethe widely-used, memory-bound Sparse Matrix Vector Multiplication (SpMV)kernel.  This paper provides the first comprehensive analysis of SpMV on a real-worldPIM architecture, and presents SparseP, the first SpMV library for real PIMarchitectures. We make two key contributions. First, we design efficient SpMValgorithms to accelerate the SpMV kernel in current and future PIM systems,while covering a wide variety of sparse matrices with diverse sparsitypatterns. Second, we provide the first comprehensive analysis of SpMV on a realPIM architecture. Specifically, we conduct our rigorous experimental analysisof SpMV kernels in the UPMEM PIM system, the first publicly-availablereal-world PIM architecture. Our extensive evaluation provides new insights andrecommendations for software designers and hardware architects to efficientlyaccelerate the SpMV kernel on real PIM systems. For more information about ourthorough characterization on the SpMV PIM execution, results, insights and theopen-source SparseP software package [26], we refer the reader to the fullversion of the paper [3, 4]. The SparseP software package is publicly andfreely available at https://github.com/CMU-SAFARI/SparseP.

Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Systems