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Reliability has taken centre stage in the development of high-performancecomputing processors. A Surge of interest is noticeable in recent times informulating fault and failure models, understanding failure mechanism andstrategizing fault mitigation methods for improving the reliability of thesystem. The article presents a congregation of concepts illustrated one afterthe other for a better understanding of damages caused by radiation, relevantfault models, and effects of faults. We examine the state of art faultmitigation techniques at the logical layer for digital CMOS based design andSRAM based FPGA. CMOS SRAM structure is the same for both digital CMOS andFPGA. Understanding of resilient SRAM based FPGA is necessary for developingresilient prototypes and it facilitates a faster integration of digital CMOSdesigns. At the micro-architectural and architectural layer, error detectionand recovery methods are discussed for bus-based multi-core systems. TheThrough silicon via based 3D Network on chip is the prospective solution forintegrating many cores on single die. A suitable interconnection approach forpetascale computing on many-core systems. The article presents an elaboratediscussion on fault models, failure mechanisms, resilient 3D routers, defecttolerance methods for the TSV based 3D NOC many-core systems. Core redundancy,self-diagnosis and distributed diagnosis at the hardware level are examined formany-core systems. The article presents a gamut of fault tolerance solutionsfrom logic level to processor core level in a multi-core and many-corescenario.

A Survey of fault models and fault tolerance methods for 2D bus-based multi-core systems and TSV based 3D NOC many-core systems