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As the number of deep neural networks (DNNs) to be executed on a mobilesystem-on-chip (SoC) increases, the mobile SoC suffers from the real-time DNNacceleration within its limited hardware resources and power budget. Althoughthe previous mobile neural processing units (NPUs) take advantage of low-bitcomputing and exploitation of the sparsity, it is incapable of acceleratinghigh-precision and dense DNNs. This paper proposes energy-efficient signedbit-slice architecture which accelerates both high-precision and dense DNNs byexploiting a large number of zero values of signed bit-slices. Proposed signedbit-slice representation (SBR) changes signed $1111_{2}$ bit-slice to$0000_{2}$ by borrowing a $1$ value from its lower order of bit-slice. As aresult, it generates a large number of zero bit-slices even in dense DNNs.Moreover, it balances the positive and negative values of 2's complement data,allowing bit-slice based output speculation which pre-computes high order ofbit-slices and skips the remaining dense low order of bit-slices. The signedbit-slice architecture compresses and skips the zero input signed bit-slices,and the zero skipping unit also supports the output skipping by masking thespeculated inputs as zero. Additionally, the heterogeneous network-on-chip(NoC) benefits the exploitation of data reusability and reduction oftransmission bandwidth. The paper introduces a specialized instruction setarchitecture (ISA) and a hierarchical instruction decoder for the control ofthe signed bit-slice architecture. Finally, the signed bit-slice architectureoutperforms the previous bit-slice accelerator, Bit-fusion, over $\times3.65$higher area-efficiency, $\times3.88$ higher energy-efficiency, and $\times5.35$higher throughput.

Energy-efficient Dense DNN Acceleration with Signed Bit-slice Architecture