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Sub/Near-threshold static random-access memory (SRAM) design is crucial foraddressing the memory bottleneck in energy-constrained applications. However,the high integration density and reliability under process variations demand anaccurate estimation of extremely small failure probabilities. To capture such arare event in memory circuits, the time and storage overhead of conventionalMonte Carlo (MC) simulations cannot be tolerated. On the other hand, classicanalytical methods predicting failure probabilities from a physical expressionbecome inaccurate in the sub/near-threshold region due to the assumeddistribution or the oversimplified drain current model for nanoscale devices.This work first proposes a simple but efficient drain current model to describethe drain-induced barrier lowering effect at low voltages. Based on that, theprobability density functions of the interest metrics in SRAM are derived. Twoanalytical models are then put forward to evaluate SRAM dynamic stabilitiesincluding access and write-time failures. The proposed models can be extendedeasily to different types of SRAM with different read/write assist circuits.The models are validated against MC simulations across different operatingvoltages and temperatures. The average relative errors at 0.5V VDD are only8.8% and 10.4% for the access-time and write failure models respectively. Thesize of required data samples is 43.6X smaller than that of thestate-of-the-art method.

A Timing Yield Model for SRAM Cells in Sub/Near-threshold Voltages Based on A Compact Drain Current Model