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Sparsity is an intrinsic property of convolutional neural network(CNN) andworth exploiting for CNN accelerators, but extra processing comes with hardwareoverhead, causing many architectures suffering from only minor profit.Meanwhile, systolic array has been increasingly competitive on CNNsacceleration for its high spatiotemporal locality and low hardware overhead.However, the irregularity of sparsity induces imbalanced workload under therigid systolic dataflow, causing performance degradation. Thus, this paperproposed a systolicarray-based architecture, called Sense, for sparse CNNacceleration by model-hardware co-design, achieving large performanceimprovement. To balance input feature map(IFM) and weight loads acrossProcessing Element(PE) array, we applied channel clustering to gather IFMs withapproximate sparsity for array computation, and co-designed a load-balancingweight pruning method to keep the sparsity ratio of each kernel at a certainvalue with little accuracy loss, improving PE utilization and overallperformance. Additionally, Adaptive Dataflow Configuration is applied todetermine the computing strategy based on the storage ratio of IFMs andweights, lowering 1.17x-1.8x DRAM access compared with Swallow and furtherreducing system energy consumption. The whole design is implemented onZynqZCU102 with 200MHz and performs at 471-, 34-, 53- and 191-image/s forAlexNet, VGG-16, ResNet-50 and GoogleNet respectively. Compared against sparsesystolic-array-based accelerators, Swallow, FESA and SPOTS, Sense achieves1x-2.25x, 1.95x-2.5x and 1.17x-2.37x performance improvement on these CNNsrespectively with reasonable overhead.

Sense: Model Hardware Co-design for Accelerating Sparse CNN on Systolic Array