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This paper presents a design for test (DFT)architecture for fast and scalabletesting of array multipliers (MULTs). Regardless of the MULT size, our proposedtestable architecture, without major changes in the original architecture,requires only five test vectors. Test pattern generation (TPG) is done bycombining C-testability, bijectivity and deterministic TPG methods.Experimental results show 100% fault coverage for single stuck-at faults. Theproposed method requires minor testability hardware insertion into themultiplier with extra delay and area overhead of less than 0.5% for a 64-bitmultiplier.

Testable Array Multipliers for a Better Utilization of C-Testability and Bijectivity