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FPGA-based accelerators are becoming more popular for deep neural network dueto the ability to scale performance with increasing degree of specializationwith dataflow architectures or custom data types. To reduce the barrier forsoftware engineers and data scientists to adopt FPGAs, C++- and OpenCL-baseddesign entries with high-level synthesis (HLS) have been introduced. Theyprovide higher abstraction compared to register-transfer level (RTL)-baseddesign. HLS offers faster development time, better maintainability and moreflexibility in code exploration, when evaluating options for multi-dimensiontensors, convolutional layers or parallelism. Thus, HLS has been adopted by DNNaccelerator generation frameworks such as FINN and hls4ml.  In this paper, we present an alternative backend RTL library for FINN. Weinvestigate and evaluate, across a spectrum of design dimensions, an RTL-basedimplementation versus the original HLS variant. We show that for smaller designparameters, RTL produces significantly smaller circuits. For larger circuits,however, the look-up table (LUT) count of RTL-based design is slightly higher,up to around $15\%$. On the other hand, HLS consistently requires moreflip-flops (FFs) (orders-of-magnitude increase) and block RAMs (BRAMs)($2\times$ more). This also impacts the critical path delay, with RTL producingsignificantly faster circuits, up to $80\%$. Furthermore, RTL also benefitsfrom at-least a $10\times$ reduction in synthesis time. Finally the resultswere practically validated using a real-world use case of a multi-layerperceptron (MLP) network used in network intrusion detection. Overall, sinceHLS frameworks code-generate the hardware design, the benefits of the ease inthe design entry is less important as compared to synthesis time reductiontogther with resource benefits, this might make the RTL abstraction anattractive alternative.

On the RTL Implementation of FINN Matrix Vector Compute Unit