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Power estimation is the basis of many hardware optimization strategies.However, it is still challenging to offer accurate power estimation at an earlystage such as high-level synthesis (HLS). In this paper, we propose PowerGear,a graph-learning-assisted power estimation approach for FPGA HLS, whichfeatures high accuracy, efficiency and transferability. PowerGear comprises twomain components: a graph construction flow and a customized graph neuralnetwork (GNN) model. Specifically, in the graph construction flow, we introducebuffer insertion, datapath merging, graph trimming and feature annotationtechniques to transform HLS designs into graph-structured data, which encodeboth intra-operation micro-architectures and inter-operation interconnectsannotated with switching activities. Furthermore, we propose a novelpower-aware heterogeneous edge-centric GNN model which effectively learnsheterogeneous edge semantics and structural properties of the constructedgraphs via edge-centric neighborhood aggregation, and fits the formulation ofdynamic power. Compared with on-board measurement, PowerGear estimates totaland dynamic power for new HLS designs with errors of 3.60% and 8.81%,respectively, which outperforms the prior arts in research and the commercialproduct Vivado. In addition, PowerGear demonstrates a speedup of 4x over Vivadopower estimator. Finally, we present a case study in which PowerGear isexploited to facilitate design space exploration for FPGA HLS, leading to aperformance gain of up to 11.2%, compared with methods using state-of-the-artpredictive models.

PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs