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Many fabless semiconductor companies outsource their designs to third-partyfabrication houses. As trustworthiness of chain after outsourcing includingfabrication houses is not established, any adversary in between, with maliciousintent may tamper the design by inserting Hardware Trojans (HTs). Detection ofsuch HTs is of utmost importance to assure the trust and integrity of thechips. However, the efficiency of detection techniques based on side-channelanalysis is largely affected by process variations. In this paper, amethodology for detecting HTs by analyzing the delays of topologicallysymmetric paths is proposed. The proposed technique, rather than depending ongolden ICs as a reference for HT detection, employs the concept ofself-referencing. In this work, the fact that delays of topologically symmetricpaths in an IC will be affected similarly by process variations is exploited. Aprocedure to chose topologically symmetric paths that are minimally affected byprocess variations is presented. Further, a technique is proposed to createtopologically symmetric paths by inserting extra logic gates if such paths donot exist in the design intrinsically. Simulations performed on ISCAS-85benchmarks establish that the proposed method is able to achieve a truepositive rate of 100% with a false positive rate less than 3%. In ourexperimentation, We have considered the maximum of 15% intra-die and 20%inter-die variations in threshold voltage (Vth).

Variability aware Golden Reference Free methodology for Hardware Trojan Detection Using Robust Delay Analysis