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Heterogeneous computers integrate general-purpose host processors withdomain-specific accelerators to combine versatility with efficiency and highperformance. To realize the full potential of heterogeneous computers, however,many hardware and software design challenges have to be overcome. Whilearchitectural and system simulators can be used to analyze heterogeneouscomputers, they are faced with unavoidable compromises between simulation speedand performance modeling accuracy. In this work we present HEROv2, anFPGA-based research platform that enables accurate and fast exploration ofheterogeneous computers consisting of accelerators based on clusters of 32-bitRISC-V cores and an application-class 64-bit ARMv8 or RV64 host processor.HEROv2 allows to seamlessly share data between 64-bit hosts and 32-bitaccelerators and comes with a fully open-source on-chip network, a unifiedheterogeneous programming interface, and a mixed-data-model, mixed-ISAheterogeneous compiler based on LLVM. We evaluate HEROv2 in four case studiesfrom the application level over toolchain and system architecture down toaccelerator microarchitecture. We demonstrate how HEROv2 enables effectiveresearch and development on the full stack of heterogeneous computing. Forinstance, the compiler can tile loops and infer data transfers to and from theaccelerators, which leads to a speedup of up to 4.4x compared to the originalprogram and in most cases is only 15 % slower than a handwrittenimplementation, which requires 2.6x more code.

HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing