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Deployment of modern TinyML tasks on small battery-constrained IoT devicesrequires high computational energy efficiency. Analog In-Memory Computing (IMC)using non-volatile memory (NVM) promises major efficiency improvements in deepneural network (DNN) inference and serves as on-chip memory storage for DNNweights. However, IMC's functional flexibility limitations and their impact onperformance, energy, and area efficiency are not yet fully understood at thesystem level. To target practical end-to-end IoT applications, IMC arrays mustbe enclosed in heterogeneous programmable systems, introducing new system-levelchallenges which we aim at addressing in this work. We present a heterogeneoustightly-coupled clustered architecture integrating 8 RISC-V cores, an in-memorycomputing accelerator (IMA), and digital accelerators. We benchmark the systemon a highly heterogeneous workload such as the Bottleneck layer from aMobileNetV2, showing 11.5x performance and 9.5x energy efficiency improvements,compared to highly optimized parallel execution on the cores. Furthermore, weexplore the requirements for end-to-end inference of a full mobile-grade DNN(MobileNetV2) in terms of IMC array resources, by scaling up our heterogeneousarchitecture to a multi-array accelerator. Our results show that our solution,on the end-to-end inference of the MobileNetV2, is one order of magnitudebetter in terms of execution latency than existing programmable architecturesand two orders of magnitude better than state-of-the-art heterogeneoussolutions integrating in-memory computing analog cores.

A Heterogeneous In-Memory Computing Cluster For Flexible End-to-End Inference of Real-World Deep Neural Networks